In high-speed data transfer, the clock data recovery (CDR) technique to extract a clock from received data is known. In the CDR technique, a PLL generates multiphase clocks the phases of which are different by a predetermined angle from another (e.g., four-phase clocks the phases of which are different by 90° from another). A phase interpolator (PI) uniformly shifts the phase of a multiphase clock while keeping the phase difference in accordance with a PI code and generates a multiphase sampling clock for taking in data. A data latch circuit latches differential input data with a multiphase sampling clock. A de-serializer (DES) converts the data that is taken in with a multiphase sampling clock into parallel data and generates a plurality of data columns. A digital filter (DF) detects a phase shift of the multiphase sampling clock with respect to the differential input data from the plurality of data columns and changes the PI code so as to eliminate the phase shift. By repeating the feedback operation such as this, the difference between the phase of the differential input data and the phase of the multiphase sampling clock converges to zero. A state where the feedback operation is effective and the phase difference is close to zero is referred to as a locked state.
In the CDR circuit, in the case where the frequency of the differential input data differs from the frequency of the multiphase sampling clock by an infinitesimal amount, the phase difference changes resulting from the frequency difference, but the value of the PI code gradually changes to follow up this change, and therefore, the state where the phase difference is substantially zero is maintained.
In the CDR circuit, if the change in phase difference is gradual, the change is followed up as described above and the locked state is maintained, but if a rapid change in phase difference occurs, the state deviates from the locked state and there is a case where it is not possible to follow up the change. The rate of change that can be followed up is determined by the performance of the feedback system of the CDR circuit and can be adjusted by the gain of the digital filter, but if the rate of change that can be followed up is increased, the fluctuations in the locked state become large. In general, the jitter amount in data transfer is determined by the specifications of the data transfer system to which the CDR circuit is applied, and therefore, the gain of the digital filter is set in accordance therewith.
However, there is a case where a large jitter (time interval error (TIE)) exceeding a prescribed value occurs temporarily due to fluctuations in power source or noise. At this time, the CDR circuit operates so as to follow up the large fluctuations in the TIE, but the state deviates from the locked state and a synchronization error occurs because it is not possible to follow up the fluctuations. The CDR circuit repeats the feedback operation after that, but it is not possible to follow up the movement of the TIE, and therefore, a synchronization error occurs frequently, and even after the TIE fades away, the time until the locked state is resumed is lengthened. Because of this, also after the TIE fades away, the synchronization error remains for a while.
The large TIE such as described above frequently occurs at the time of start of reception or transmission, at the time of switching of transfer directions, etc., and therefore, the large TIE frequently occurs at the synchronization pattern portion at the top of a packet. In this case, the locked state of the CDR circuit deviates and it takes time to resume the locked state, and therefore, there occurs a situation in which the locked state is not resumed before the data portion arrives.